Method for patterning hfo2-containing dielectric

ABSTRACT

A wafer has a trench, a STI layer formed in the trench, an HfO2-containing gate dielectric covering the wafer and the STI layer, a gate electrode formed on the HfO2-containing gate dielectric, and at least a spacer formed beside the gate electrode. An ion bombardment utilizing Ar, He, O2, CHF3 or mixture thereof is performed to convert the exposed HfO2-containing gate dielectric to an intergraded layer, and a wet chemical is utilized to remove the intergraded layer.

CROSS REFERENCE TO RELATED APPLICATIONS

This is a continuation application of U.S. patent application Ser. No.11/160,629, filed Jun. 30, 2005, which itself is a divisional ofapplication Ser. No. 10/710,581 filed Jul. 22, 2004.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a method for patterning an HfO2-containingdielectric, and more particularly, to a method for patterning anHfO2-containing gate dielectric without damaging STI positioned on thesame wafer.

2. Description of the Prior Art

For realizing the low power MOS transistor at the 65 nm node and beyond,it is necessary to reduce the gate leakage current for thinner gatedielectrics. The introduction of high-k gate material would beadvantageous for extending current MOS technology. After several yearsof work, many research groups are now focusing on hafnium (Hf) basedmaterial and are evaluating the natural of these materials extensively.Among the considerable Hf-based materials, HfO2 is often evaluated to becombined into a metal gate structure.

However, HfO2-containing dielectric (including HfO2, HfSiO, HfSiON,HfAIO, and so on) is known for more difficult to be pattern etchedcomparing to SiO2 based dielectric. The conventional method of etchingthe HfO2-containing dielectric involves using a strong acid, such as 49%HF solution. When using the 49% HF solution to etch the HfO2-containingdielectric, a SiO2 layer, such as a shallow trench isolation (STI)layer, will be also removed. Furthermore, the etching rate of the SiO2layer is much higher than that of the HfO2-containing dielectric, andthe SiO2 layer will be seriously damaged while patterning theHfO2-containing dielectric.

Another conventional method of etching the HfO2-containing dielectric isusing a high insert gas plasma with more than 60% Ar. The insert gasplasma has no selectivity while etching, and may also result in the SiO2layer being damaged during over-etch.

Please refer to FIGS. 1 and 2, which show a conventional etching processof the HfO2-containing dielectric. An STI layer 18 is formed on a wafer10, and an HfO2-containing gate dielectric 12 covers the wafer 10 andthe STI layer 18. A gate electrode 16 is formed on the HfO2-containinggate dielectric 12, and two spacers 14 are formed beside the gateelectrode 16. As shown in FIG. 2, the conventional etching process suchas using the strong acid or the insert gas plasma is performed to removeportions of the HfO2-containing gate dielectric 12. The etchingselectively between the HfO2-containing gate dielectric 12 and the STIlayer 18 is too low to bring serious damages atop the STI layer 18. As aresult, the isolation effect of the STI layer 18 is reduced.

SUMMARY OF THE INVENTION

It is therefore a primary objective of the claimed invention to providea method for patterning the HfO2-containing gate dielectric withoutdamaging the SiO2 layer to solve the above-mentioned problem.

According to the claimed invention, a method for patterning anHfO2-containing gate dielectric comprises providing a wafer having atrench, a STI layer formed in the trench, the HfO2-containing gatedielectric covering the wafer and the STI layer, a gate electrode formedon the HfO2-containing gate dielectric, and at least a spacer formedbeside the gate electrode. Following that, the wafer is preheated and abromine-rich gas plasma is provided to remove portions of theHfO2-containing gate dielectric.

According to the claimed invention, a method for patterning anHfO2-containing gate dielectric comprises providing a wafer having atrench, a STI layer formed in the trench, the HfO2-containing gatedielectric covering the wafer and the STI layer, a gate electrode formedon the HfO2-containing gate dielectric, and at least a spacer formedbeside the gate electrode. Following that, an ion bombardment utilizingAr, He, O2, CHF3, or mixture thereof is used to convert the exposedHfO2-containing gate dielectric to an intergraded layer. A wet chemicalis used to remove the intergraded layer.

It is an advantage of the claimed invention that the bromine-rich gasplasma has a high selectivity between the HfO2-containing dielectric andthe SiO2layer, so that the HfO2-containing dielectric can be etchedwithout damaging the SiO2layer.

It is another advantage of the claimed invention that the nitrogen ionbombardment can convert the HfO2-containing dielectric to the Hf3N4layer and the wet chemical has a high selectivity between the Hf3N4 andSiO2layers, so that the HfO2-containing dielectric can be etched withoutdamaging the SiO2layers.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a wafer before performing a gatedielectric patterning process thereon according to the prior art;

FIG. 2 is a schematic diagram of a wafer after performing a gatedielectric patterning process thereon according to the prior art;

FIG. 3 is a schematic diagram of a wafer after performing a gatedielectric patterning process thereon according to the presentinvention; and

FIG. 4 is a schematic diagram of a wafer after performing a gatedielectric patterning process thereon according to a second embodimentof the present invention.

DETAILED DESCRIPTION

Please refer to FIG. 3, which shows a result of performing a patterningprocess according to a first embodiment of the present invention. In thefirst embodiment of the present invention, a bromine-rich gas plasma isutilized to accomplish the requirement of etching the HfO2-containingdielectric with a high selectivity. In this embodiment, a MOS transistorfabrication is used to explain the present invention. Before the etchingprocess, the half-manufactured wafer is similar to that of the prior artas shown in FIG. 1. For example, the STI layer 18 is formed on the wafer10, and the HfO2-containing gate dielectric 12 covers the wafer 10 andthe STI layer 18. The gate electrode 16 is formed on the HfO2-containinggate dielectric 12, and two spacers 14 are formed beside the gateelectrode 16. The STI layer 18 and the spacer 14 may be formed of SiO2,and the gate electrode 16 may be formed of TaN or TiN.

Then, the wafer 10 is placed into a reactor and is preheated to 200° C.or over 200° C. The reactor can be any type of plasma reactors, such asthe parallel plate, the reactive ion etcher (RIE), the inductivelycoupled plasma (ICP), or the electron cyclotron resonance etcher (ECR),and the preheating procedure can utilize a lamp tray or a non-reactivegas plasma to preheat the wafer 10.

After the wafer 10 is preheated to 200° C. or over 200° C., thebromine-rich gas plasma is supplied into the reactor to remove portionsof the HfO2-containing gate dielectric 12. The bromine-rich gas plasmacan be a Br2 plasma, a HBr plasma, or a mixture of a Br2 plasma and aHBr plasma, and concentration of the bromine-rich gas plasma is higherthan 30%. On the wafer surface, the bromine-rich gas plasma will reactwith the HfO2-containing gate dielectric 12 and produce a volatileproduct HfBr4. At the elevated temperature (≧200° C.), HfBr4 is volatileand can be taken out by the pumping system. After removing portions ofthe HfO2-containing gate dielectric 12, the STI layer 18 is exposed.Since the bromine-rich gas plasma etches the SiO2material of the STIlayer 18 much slower than the HfO2-containing gate dielectric 12, theSTI layer 18 will be almost undamaged. In addition, a sacrifice layer(not shown) can be further formed on the gate electrode 16 beforeperforming the patterning process to protect the gate electrode 16. Thesacrifice layer may be formed of SiO2.

Furthermore, in other embodiments of the present invention, additivegases, such as Ar, N2, He, O2, CHF3, etc., can be introduced into thereactor to assist uniform etching of the HfO2-containing gate dielectric12. It is also worthy of notice that the present invention is notlimited to pattern the HfO2-containing gate dielectric. The presentinvention is also applicable in any etching process relating to patternHfO2-containing dielectric. For example, a wafer having anHfO2-containing dielectric is provided, and the wafer is preheated to apredetermined temperature. Following that, a bromine-rich gas plasma isprovided to remove portions of the HfO2-containing dielectric, thusproviding a high etching selectivity in etching HfO2.

Another embodiment of the present invention is utilizing a nitrogen ionbombardment to convert the exposed HfO2-containing dielectric to anHf3N4 (Hafnium Nitride) layer and then utilizing a wet chemical, such asphosphoric acid, to remove the Hf3N4 layer. Please refer to FIG. 4,which shows the patterning process of the second embodiment. A nitrogenion bombardment is performed on the half-manufactured wafer 10, and theexposed HfO2-containing gate dielectric 12 is converted to an Hf3N4layer 20. While performing the nitrogen ion bombardment, a nitrogen gasor a nitrogen-contained gas can be used to produce the nitrogen ions.The regions covered by the gate electrode 16 and the spacers 14 areprotected and retain the HfO2-containing material. Selectively, asacrifice layer (not shown) can be also formed on the gate electrode 1 6before performing the nitrogen ion bombardment to protect the gateelectrode 16.

After the nitrogen ion bombardment, the Hf3N4 layers 20 are formedbeside the portion of HfO2-containing gate dielectrics 12 under the gateelectrode 16 and the spacers 14. The Hf3N4 layers 20 are easily etchedby the phosphoric acid. In this embodiment, a H3PO4 solution is utilizedto remove the Hf3N4 layers 20, but the H3PO4 solution etches neither theSiO2layer nor the Si layer. The STI layers 18 will be almost undamagedafter the Hf3N4 layers 20 is removed. In addition, for speeding theremoving process, the H3PO4 solution can be maintained at thetemperature 50° C.-300° C. It is also worthy of notice that the presentinvention is not limited to pattern the HfO2-containing gate dielectric.The present invention is also applicable in any etching process relatingto pattern HfO2-containing dielectric. For example, a wafer having anHfO2-containing dielectric is provided, and a nitrogen ion bombardmentis used to convert portions of the HfO2-containing dielectric to anHf3N4 layer. Following that, a wet chemical such as phosphoric acid isused to remove the Hf3N4 layer, thus providing a high etchingselectivity in etching HfO2.

In contrast to the prior art, the present invention has a high etchingselectivity between the HfO2-containing material and the SiO2material,so that the STI layer can be retained complete after the gate dielectricis removed.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

1. A method for patterning an HfO2-containing gate dielectric, themethod comprising: providing a wafer having a trench, a STI layer formedin the trench, the HfO2-containing gate dielectric covering the waferand the STI layer, a gate electrode formed on the HfO2-containing gatedielectric, and at least a spacer formed beside the gate electrode;performing an ion bombardment with Ar, He, O2, CHF3or mixture thereof toconvert the exposed HfO2-containing gate dielectric to an intergradedlayer having a higher etching selectivity than HfO2; and utilizing a wetchemical to remove the intergraded layer.
 2. The method of claim 1wherein the STI layer comprises SiO2.
 3. The method of claim 1 whereinthe spacer comprises SiO2.
 4. The method of claim 1 wherein the gateelectrode comprises TaN or TiN.
 5. The method of claim 1 wherein themethod comprises utilizing a nitrogen gas or a nitrogen-contained gas toperform the ion bombardment.
 6. The method of claim 1 wherein theintergraded layer is removed at temperature between 50° C. and 300° C.7. A method for etching an HfO2-containing dielectric, the methodcomprising: providing a wafer having the HfO2-containing dielectric;performing an ion bombardment with Ar, He, O2, CHF3or mixture thereof toconvert portions of the HfO2-containing dielectric to an intergradedlayer; and utilizing a wet chemical to remove the intergraded layer. 8.The method of claim 7 wherein the method comprises utilizing a nitrogengas or a nitrogen-contained gas to perform the ion bombardment.
 9. Themethod of claim 7 wherein the intergraded layer is removed attemperature between 50° C. and 300° C.